Implementation of Blake Algorithm Using Pipelining in Fpga

This paper proposes the Pipelined SHA-3 BLAKE algorithm, running on an FPGA with the intention of developing the optimization in FPGA for BLAKE algorithm. Secured hash algorithm-3(SHA-3) BLAKE algorithm is a family of cryptographic hash function published by the National Institute of Standards and Technology (NIST). To implement BLAKE algorithm we have utilized VHDL, where we introduce the pipelining. Pipelining executes single task per clock cycle which improves the efficiency of the algorithm. The simulation is done with the usage of model sim and synthesis it on FPGA Spartan 3E using Xilinx software. Our VHDL implementation executed on BLAKE algorithm occupies 30% percentage of FPGA’s area.